16-Gbit MLC NAND flash a step up

In early 2006, IM Flash Technologies (IMFT)-- progeny of a pairing of Micron Technology Inc. and Intel Corp.--entered the market with a splash. Combining Intel's NOR multilevel-cell (MLC) flash technology and Micron's DRAM and NAND flash manufacturing efficiency and innovation--and with the backing of a formidable intellectual-property (IP) portfolio from both parents--IMFT's first product, delivered that same year, had the market abuzz with expectation.

The cutting-edge processes used by IMFT can dramatically change the way consumer electronics are built and used. Evolutionary products such as the Intel-backed Robson flash cache technology and hybrid SSD/HD systems (backed by Microsoft, Sandisk and Seagate) are enabled by these high-density, high-performance flash devices. These technologies will likely begin to appear in memory-hungry products such as desktop and notebook computers. Tiny MLC NAND flash devices can store huge amounts of data, and they need no power to retain it. Because flash memory has no moving parts, it is much more shock-tolerant than the hard-disk drives it will ultimately replace. This sturdiness makes it ideal for mobile applications, especially in the automotive field (such as GPS navigation systems and high-end automobile entertainment systems).

Flash memory implemented in a hybrid HD or Robson flash cache can access data more than 100 times faster than traditional USB flash drives. This directly benefits the mobility and functionality of mobile devices such as cell phones and PDAs. Other products, including USB drives, MP3 players, digital cameras, navigation systems and data recorders, will benefit from these next-generation flash memory devices as well.

When loaded from a flash memory device instead of a hard-disk drive, a typical Microsoft Word document can be opened in less than one-tenth of a second (and a very large document in less than 5 seconds),while booting Windows XP could take less than 15 seconds--and all this with the inherent reliability afforded by a total of moving parts. To put this further into perspective, consider that a digital camera memory card could read and write about 1,000 images each day for seven years before needing to be replaced. Such cards will likely be reused in replacement cameras before they actually wear out.

Departures at 50 nm
To meet the high expectations of the Intel-Micron venture, IMFT had to close the technology gap set by its key competitors: Toshiba and Samsung. In the third quarter of 2006, IMFT went a long way toward doing just that with the release of the 50-nm, 4-Gbit SLC NAND flash product, analyzed in detail by Semiconductor Insights in September 2006. It was evident from the analysis that IMFT had departed from the traditional strategies used by both parent companies. Micron had accommodated the biggest change by evolving from a cost and manufacturing innovator into a leading-edge innovator.

But IMFT fell a bit short of closing the gap completely. Rival Toshiba, which traditionally used MLC technology to optimize memory densities, was able to achieve an impressive 56.5-Mbit/mm² memory bit density on its 8-Gbit, 70-nm flash process. IMFT's 4-Gbit SLC flash device, even with its advanced 50-nm technology, fell just short of Toshiba's 41.8-Mbit/mm² rating.

IMFT's 4-Gbit device was fabricated in a triple-metal, triple-poly, 50-nm CMOS process. Although Micron was known for its early implementation of copper in its DRAM interconnect process, IMFT delivered a more conservative aluminum interconnect process for metal 2 and metal 3, accompanied by a novel tungsten via-first dual damascene for metal 1.

The unusual, shallow-trench isolation process used for the 4-Gbit device enabled implementation of a triple-gate oxide process with an interpolysilicon capacitor structure. This was an innovative approach to isolation: The gate dielectrics were formed before the formation of the active-area hard mask/STI polish stop layer. In a further departure from conventional approaches, IMFT used a polysilicon hard mask (likely with a nitride capping layer) in place of the conventional silicon nitride.

After STI etching, filling and planarization, an embedded polysilicon layer coplanar with the isolation surface was formed. In areas where a thick high-voltage oxide was grown, this polysilicon layer was used as the lower plate of an interpolysilicon capacitor with a high-quality CMP-finished interface. Masked removal of the subsequently deposited ONO capacitor dielectric provided contact regions for the second poly layer to the lower capacitor plate. In areas where the transistor gate electrodes were to be formed, the ONO layer was completely removed.

16-Gbit extreme makeover
IMFT's "next-generation" 50-nm, 16-Gbit MLC process is, for all practical purposes, a relaxed "40-something-nm" process technology. Like its predecessor, the device is fabricated using a triple-metal, triple-poly process. At first glance, the announcement of the 50-nm, 16-Gbit MLC device appeared innocuous and even tardy (considering the time elapsed since the introduction of the 4-Gbit SLC flash product). But beauty is only skin deep; truly understanding how significantly different this product is from its earlier 50-nm cousin requires a look inside the device.

First, IMFT engineers have migrated from an aluminum-based interconnect to a copper interconnect technology. This new process will enable easier scaling of the metallization layers to accommodate the approximately 40-nm designs. Metal 1, formed using a via-first tungsten dual damascene process, has simply been transferred from the 4-Gbit version to the new 16-Gbit flash device; we'll see whether this is reused for the second time at 40 nm.

IMFT has also modified the shallow-trench isolation integration sequence. The modifications provide scalability to the active area pitch in the memory array (something critical for positioning the technology for IMFT's push to the next process node) and are studied in more detail by Semiconductor Insights. Interestingly, although the modifications allow scaling, some steps in the sequence do not appear to be technically advantageous. One cannot help but wonder if this approach was intended to sidestep other flash memory suppliers' own proprietary self-aligned STI process sequences.

Finally, a nearly 20 percent reduction of the array poly width in this device should reduce capacitive coupling in the array and improve overall power and speed performance. This should further position the process for scaling to the next technology node, especially if low-k materials are used to decrease coupling further in the memory array.

Facing off
Comparing Toshiba's and IMFT's 16-Gbit MLC NAND flash devices, we see a different story unfolding. Toshiba delivered an impressive, 94.5-Mbit/mm² bit density rating on its 16-Gbit, 56-nm MLC device; but IMFT, at 98.7 Mbit/mm² on its 16-Gbit MLC device, has surpassed Toshiba in memory bit density and has almost equaled rival Samsung's 101.7 Mbit/mm² delivered on its 51-nm, 16-Gbit NAND device.

Considering that IMFT has already introduced a 20 percent reduction in its floating-gate width, it would not be surprising to see 40-nm devices sampling early next year using a slightly modified version of the current 50-nm process. From a big-picture point of view, each technology migration brings us another step closer to more cost-effective solid-state drives. When we turn that corner, it will surely spawn new consumer products that will in turn create demand for more capacity in the semiconductor technology sector. Since I've still got a few years of gainful employment remaining, I'm all for that! n

John Boyd (johnb@semiconductor.com) is a technology analyst at Semiconductor Insights (Kanata, Ontario), a Techinsights company. He holds more than 60 U.S. patents and has more than 40 pending.