Othello chip suits 3G TD-SCDMA wireless handsets(英)

www.52RD.com　2007年7月19日　我爱研发网　eeProductCenter
Analog Devices Inc. has unveiled the latest addition to its family of Othello direct conversion radios and its broad TD-SCDMA product portfolio, the Othello-3T AD6552.
The Othello-3T AD6552 is ADI’s second-generation radio designed specifically for the 3G TD-SCDMA standard and complements all of the company’s TD-SCDMA baseband chipsets, including SoftFone-LCR and SoftFone-LCR+.
Based on the Othello direct-conversion architecture and a low-noise transmitter, AD6552 simplifies the development of the radio section of 3G wireless handsets by eliminating the SAW filters that are usually needed in the transmit path, reducing both cost and board space. In addition, the receiver section provides EVM performance that supports the requirements for HSDPA and includes a fully-automatic DC offset control.
AD6552 integrates almost all of the necessary components for a handset radio design (VCOs, tank circuits, loop filters and power management) on a single chip. Component count for a dual-band radio is reduced by nearly 40 percent compared to the previous two-chip Othello-W single-band radio for TD-SCDMA, according to ADI.
The Othello-3T AD6552 direct-conversion CMOS RF transceiver provides a complete transmit/receive product for TD-SCDMA-based mobile terminals. The receiver section includes high-performance single-ended low-noise amplifiers (LNAs) covering the 1,900- and 2,000MHz bands. A direct-down-converting quadrature mixer driven by an on-chip fractional-N PLL synthesizer deliver baseband I and Q (In-phase and Quadrature) signals to a variable-gain amplifier (VGA) and programmable low-pass filter stages with DC offset correction.
The transmitter section consists of a fractional PLL synthesizer, a high performance VGA and quadrature modulator driving a common wideband output stage, as well as a true-rms RF power detector and on-chip DAC for power amplifier control.
Othello-3T AD6552 is sampling now in a 6mm x 6mm 40-lead lead-frame chip scale package.