Massively multicore processor runs Linux

Massively multicore processor runs LinuxAug. 20, 2007
Astartup founded by an MIT professor claims to have "solved thefundamental challenges associated with multicore scalability." Tilera‘sfirst products include a 64-core Tile64 SoC (system-on-chip), PCIeExpress add-in board for networking and video-processing applications,multicore-optimized Linux libraries, and an Eclipse-based multicoredevelopment environment toolsetFabbedon 90nm process technology at TMSC, the Tile64 chip is "the first in afamily of chips that can scale to hundreds and even thousands ofcores," Tilera said. The company plans to bake a 120-core version on65nm technology in the future, it added.
The Tile64 is basedon a proprietary VLIW (very long instruction word) architecture, onwhich a MIPS-like RISC architecture is implemented in microcode. Ahypervisor enables each core to run its own instance of Linux -- orother OSes, once they become available. Alternatively, the whole chipcan run Tilera‘s 64-way SMP (symmetrical multiprocessing)implementation.

Tilera Tile64 architecture
(Click to enlarge)
Thecrown jewel of the Tile64 architecture is a network-like "iMesh"switching interconnect said to eliminate the centralized busintersection that in previous multicore designs has limitedscalability, according to the company. Tilera‘s founder, MIT professorand serial entrepreneur Dr. Anant Agarwal, has experimented withmesh-like chip interconnects since 1996, the company said.
Eachof the Tile64‘s cores clocks between 600MHz and 900MHz; each has itsown L1 and L2 cache. L3 cache is handled in an interesting way, as BobDoud, director of marketing, explains. "We take all the L2 caches andconsider them in aggregate to be the L3 cache," he said. "It‘s highlyeffective, because if you reference your own cache, and don‘t find thedata you‘re looking for, a neighbor may have it, and that‘s faster thangoing off chip to external memory by a good ways."
The Tile64 isimplemented as a a system-on-chip (SoC) with no requirement forexternal northbridge and/or southbridge chips. This saves power, at theexpense of locking in a specific peripheral mix, essentially tying thechip to specific verticals, according to the company. Doud noted, "Wedid a lot of research, and believe we have the peripheral mix right forthe markets we are targeting -- networking and video. If we went intostorage with a new processor, we‘d add fiber and disk drive interfaces."
Tileraclaims that the Tile64 outperforms Intel‘s dual-core Xeon processor 10times, while offering 30 times better performance per Watt. Compared toTI‘s top-of-range TMS320DM648 DSP, performance per Watt is claimed tobe 40 times better.
Another touted benefit is the ability toconsolidate control- and data-plane functions on a single device, with"solid-wall" processor boundaries reinforcing security and licensingcontainment barrier. In this regard, the Tile64 chip resembles anotherheavily multicore MIPS64 chip, Cavium‘s 16-wayOcteon.
Software environment and tools
Tileraclaims that existing, "unmodified" Linux apps will build for the Tile64processor using the company‘s toolchain. The toolchain includes acompiler licensed from SGI and based on MIPSpro.
Alternatively,developers can port their applications to Tilera‘s iLib C library,aimed at exploiting parallelism while still supporting standard systemcalls. The approach appears to resemble that used in Intel‘sThreading Building Blocks, recently released under an open source license.
Finally,for users wishing to manually tune multi-core application performance,Tilera will offer a full "MDE" (multicore development environment)toolsuite based on Eclipse. In addition to a full IDE (integrateddevelopment environment), MDE includes a parallel debugger, along withan application profiler aimed at helping developers figure out whatparts of their code to optimize for multicore.
Tilera is indiscussions with "all major Linux support providers," Doud said,adding, "We‘ll have ecosystem announcements coming out as we line themup."
Early markets, customers, reference implementations
Thefirst Tile64 chips target network and video devices that requiresignificant application processing, such as surveillance systems, andfirewalls with deep packet inspection. Early customers in thenetworking space reportedly include 3Com and firewall vendor TopLayer,while early video customers reportedly include U.K.-basedhigh-definition videoconferencing equipment provider Codian, andBackupTV, a vendor of network-based video recording and other head-endservices for cable TV network providers.
To hasten adoption,Tilera is offering processor daughterboards implemented as PCI Expresscards with six or 12 gigabit Ethernet ports. The cards can be used inproduction systems with passive backplanes, or as targets indevelopment hosts, Doud said. He declined to specify pricing.


Tilera TILExpress-64 PCIe card and its architecture
(Click architecture diagram to enlarge)
CEODevesh Garg stated, "This is the first significant new development inchip architecture in a decade. We developed this new architecturebecause existing multicore technologies simply cannot scale. Moreover,customers have repeatedly indicated that the current multicore softwaretools are very primitive because they are based onsingle-processor-core models. We‘re introducing a revolutionaryhardware and software platform that has solved the fundamentalchallenges associated with multicore scalability."
Availability
TheTile64 is available now, in three variants differentiated by I/O mixand clock. Pricing starts at $435 in 10,000 quantities, the companysaid. Tilera‘s iLib and MDE tools, and TilExpress-64 board are alsoavailable at undisclosed pricing.
--Henry Kingman
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