神马文学网各家半导体工艺的简单比较和总结-LOGIC
来源：百度文库 编辑：神马文学网 时间：2024/04/25 15:21:23
此文非常详细的比较和总结了最有代表性的业界的各家公司的Logic工艺,仔细阅读之后就会对半导体集成电路的制造工艺有大概的认识.若要深究,则最好有一些半导体物理和工艺的基础知识.希望大家喜欢. z5\;OLJS,.‘阿果资源网(www.agpr.net)版权所有‘
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MOS technology evolved from PMOS in the 1960’s, to NMOS in 1970’s, and to CMOS in the 1980’s. CMOS technology then became the mainstream IC fabrication technology, and is now the dominant technology for IC manufacturing. IThe main advantages of CMOS are low power consumption and high-speed operation. Due to these advantages, integration of more than 100 million MOS transistors into a single CMOS chip became a reality and fast logic chips operate at a clock frequency in the gigahertz (GHz) range. The POWER4 microprocessor from IBM, for example, integrates 174 million transistors on a chip fabricated with IBM’s 0.18um SOI CMOS technology. Microprocessors from Intel and AMD are running at a clock frequency of over 2GHz. ]HjB DY}* cX.‘阿果资源网(www.agpr.net)版权所有‘
Integration of one billion transistors into a single chip will become a reality before 2010. Intel’s processor roadmap projects a one billion-transistor chip around 2007. This chip will be built on 45nm CMOS technology with transistors having a gate length of around 25nm. CMOS will remain the dominant technology as industry continues toward the scaling limit. `?\tUO2_T.‘阿果资源网(www.agpr.net)版权所有‘
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As of 2nd half of 2004, 90nm technology is at the beginning of manufacturing life cycle at a very limited number of top semiconductor manufacturers. For majority of IC manufacturers, 90nm technology is in the qualification stage or in the middle of development. ? ]sM8Bd}.‘阿果资源网(www.agpr.net)版权所有‘
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0.13um technology is now in volume production in leading IC manufacturers for high-performance and high-density products. Across the industry, however, 0.18um or older technology is still used for production of many logic products. 5 lKJll^2:.‘阿果资源网(www.agpr.net)版权所有‘
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Development of 65nm technology is now in full swing in the industry. For many companies, it is still in the early stage or in the middle of development. We are already seeing encouraging results on fully integrated 65nm logic technologies from early leaders at 65nm node. There is no sign of slowing down in scaling the logic technology to the 65nm generation. qpoV]#iW.‘阿果资源网(www.agpr.net)版权所有‘
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There are two breeds of logic technology that serve the market today. One is high- performance logic technology, and the other is platform technology. W^,S6!.‘阿果资源网(www.agpr.net)版权所有‘
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High-performance logic technology is aimed at high-speed and high-density applications such as microprocessors, graphics processors, and digital signal processors. The important goal of this kind of technology is to deliver the highest speed performance and density. Aggressive technology scaling, adoption of new processes, and good transistor and interconnect performance are the key attributes of this type of technology, as exemplified by technology from Intel, AMD, and IBM. v 7 .‘阿果资源网(www.agpr.net)版权所有‘
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The platform technology serves multiple applications, such as low power, general purpose (ASIC), RF and mixed signal, and high-performance applications. This technology is modular and flexible, and quite often features embedded memory capability such as DRAM, SRAM, and flash memory. Logic technologies for system-on-chip (SoC) applications belong to this category. For many integrated device manufacturers (IDM) and foundry companies, such as TSMC and UMC, this is the logic technology of choice. a` 9L,8Ve.‘阿果资源网(www.agpr.net)版权所有‘
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The following reviews describe the latest developments in logic technology. })xp%<`.‘阿果资源网(www.agpr.net)版权所有‘
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65nm Node Logic Technology LZPuDf~/.‘阿果资源网(www.agpr.net)版权所有‘
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During the past several years, there have been numerous publications and presentations addressing process and device issues at 65nm node. In 2002, Toshiba became the first company to bring a fully integrated 65nm technology to the public’s attention when it presented 65nm CMOS technology at IEDM 2002. A year later, NEC and Fujitsu joined the 65nm club when they presented their own 65nm logic technologies at IEDM 2003. Other companies, such as IBM, TI, Motorola, TSMC, Samsung, STMicro, presented at conferences the results of integrated 65nm process or features of their 65nm technology in 2003-2004 time frame. Intel is now said to be planning a production start in early 2005. | r ue=QZ.‘阿果资源网(www.agpr.net)版权所有‘
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65nm SoC Technology by Toshiba pEECHk.‘阿果资源网(www.agpr.net)版权所有‘
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The 65nm technology by Toshiba presented at the IEDM 2002 (N. Yanagiya, et al., pp. 57-60) is targeted for SoC application. It features embedded SRAM and DRAM with cell sizes of 0.6um**2 and 0.11um**2, respectively. The DRAM cell has a 6.5um deep trench capacitor that provides 20fF capacitance. -}K<ni6.‘阿果资源网(www.agpr.net)版权所有‘
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The MOSFET gate length is 30nm, which is realized by high-NA 193nm lithography, alternating phase shift mask (PSM), and resist slimming process. Gate dielectric is a nitrided oxide with EOT of ~10A. Poly-SiGe coupled with spike RTA provides adequate activation for gate doping. MOS transistors offer good DC performance; the drive current is 700uA/um for N-ch and 300uA/um for P-ch at Vdd=0.85V with an off-state leakage of 100nA/um. m%?V7-9!k.‘阿果资源网(www.agpr.net)版权所有‘
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At 65nm node, nickel silicide is expected to replace cobalt silicide to achieve low resistance on narrow gate poly lines and also to achieve low junction leakages. Toshiba uses NiSi in its 65nm technology and demonstrates good performance for narrow poly line resistance and junction leakage. 1?Z4 K /.‘阿果资源网(www.agpr.net)版权所有‘
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Critical mask layers are defined with high-NA 193nm lithography with alternating phase shift mask. Toshiba can offer up to 13 layers of Cu interconnect with low-k ILD with a target dielectric constant of 2.7. ut r: J.‘阿果资源网(www.agpr.net)版权所有‘
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Toshiba relies mostly on conventional processes available today, so manufacturability of its 65nm technology is well demonstrated. U(x]O/m .‘阿果资源网(www.agpr.net)版权所有‘
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65nm Technology by NEC ({o‘d=nO.‘阿果资源网(www.agpr.net)版权所有‘
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NEC’s 65nm bulk CMOS technology, presented in IEDM 2003 (Y. Nakahara, et al., pp. 281-284), was developed with emphasis on gate oxide and transistor reliability for a wide range of Vdd operation. Like Toshiba, NEC demonstrates that 65nm node can be reached by extending process technologies available at 90nm node. One new feature at 65nm node is the nickel silicide. Like Toshiba, NEC made a transition from CoSi to NiSi at 65nm node. NF? vg/{.‘阿果资源网(www.agpr.net)版权所有‘
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Gate dielectric is a plasma-nitrided gate oxide with a thickness of 1.1nm/1.35nm for 0.9V/1.2V operation. Nitrogen concentration in the gate oxide was optimized carefully to achieve acceptable gate oxide TDDB, transistor NBTI and HCI lifetime. VH:]@x//{.‘阿果资源网(www.agpr.net)版权所有‘
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The MOSFET gate length is 43nm, patterned by 193nm lithography and ARC shrink etching. NEC achieves good transistor drive currents for platform technology. At Vdd=1.2V, the drive current is 1150uA/um for N-ch and 550uA/um for P-ch with off-state leakage current of 180nA/um. These drive currents are achieved by film stress optimization (tensile stress on N-ch, neutral stress on P-ch) as well as channel, gate, and S/D extension engineering. +U@<\kIF.‘阿果资源网(www.agpr.net)版权所有‘
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65nm Technology for Mobile Multimedia Applications by Fujitsu c ;‘[W60.‘阿果资源网(www.agpr.net)版权所有‘
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Targeted for mobile multimedia applications, Fujitsu’s 65nm technology, presented at IEDM 2003 (S. Nakai, et al., pp. 285-288), focuses on interconnect parasitic capacitance reduction to achieve high-speed data transmission. [V WUqlNt>.‘阿果资源网(www.agpr.net)版权所有‘
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The use of hybrid low-k material, consisting of NSC (nano-clustering silica, a porous silica material) with k=2.25 at wire level and SiOC with k=2.9 at via level, allows Fujitsu to achieve a significant reduction in RC delay and power consumption caused by interconnect capacitance. Simulation results indicate a 25% reduction in interconnect RC delay and a 41% reduction in power consumption when compared with its 90nm technology. Optimization of BEOL provides NSC/SiOC hybrid low-k material with sufficient mechanical strength, resulting in a robust interconnect system. q?ix$nKOv.‘阿果资源网(www.agpr.net)版权所有‘
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The MOSFET features a conservative gate length of 50nm, and EOT is 2.3nm using nitrided oxide. The drive current is acceptable, but not particularly impressive at 65nm node: 830uA/um for N-ch and 350uA/um for P-ch at Vdd=1.1V with off-state leakage current of 30nA/um. @qHNE,K.‘阿果资源网(www.agpr.net)版权所有‘
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Fujitsu’s 65nm technology also features SRAM with a competitive cell size measured at 0.55um**2. A small SRAM cell is achieved by 193nm lithography with NA=0.75, attenuated PSM, and model-based OPC. k{Aj^O3gD.‘阿果资源网(www.agpr.net)版权所有‘
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Like Toshiba and NEC, Fujitsu uses NiSi at 65nm node. The back-end process uses copper interconnect, except for the top layer, for which Fujitsu uses aluminum. `kJ^zw+.‘阿果资源网(www.agpr.net)版权所有‘
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90nm Node Logic Technology ID G}ZlG.‘阿果资源网(www.agpr.net)版权所有‘
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90nm technology took the main stage in 2002. A large number of companies presented their 90nm technologies either at the Symposium on VLSI Technology in June, 2002 or at the IEDM in December, 2002. SK# (#OQoh.‘阿果资源网(www.agpr.net)版权所有‘
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At least nine companies delivered a paper on 90nm or 100nm technology in 2002. These companies include Intel, TSMC, Samsung, Sony, IBM, NEC, Toshiba, Mitsubishi, Matsushita, Fujitsu, and Motorola. For these companies, a major development milestone was reached in this technology node during the 2001-2002 timeframe. However, these are the first-phase development results, and are by no means production ready at the time of presentation. ] A+?EE2/.‘阿果资源网(www.agpr.net)版权所有‘
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A few more 90nm technology presentations followed in 2003, at the Symposium on VLSI Technology and at IEDM. TI joined the 90nm club six months after the first wave of 90nm companies, when it presented 90nm logic technology at the Symposium on VLSI Technology in June, 2003. In December, 2003 at IEDM, Intel described its 90nm technology for volume manufacturing in its late paper presentation. TSMC presented 90nm SoC technology for mixed-signal and RF applications. L>R P-x>.‘阿果资源网(www.agpr.net)版权所有‘
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Intel’s 90nm technology presented at IEDM 2003 is a follow-up to its 90nm paper presented in IEDM 2002. However, it should be noted that, rather than a refinement of its 2002 technology, the volume manufacturing technology described in the 2003 paper was drastically different from 2002 version in the implementation of strained-Si. For the volmue manufacturing 90nm technology, Intel abandons the strained-Si channel approach that it highlighted in the 2002 paper, and opts for a less aggressive strain engineering. (For more details, see 90nm Logic Technology by Intel, 2003 Version below.) q; ][5.‘阿果资源网(www.agpr.net)版权所有‘
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90nm Logic Technology by Intel, 2003 Version m1M t#@,$.‘阿果资源网(www.agpr.net)版权所有‘
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At IEDM 2003, Intel presented 90nm volume manufacturing technology in a late paper (T. Ghani, et al., pp. 978-980). This is a more mature 90nm technology than the one it presented a year ago and also has one significant difference from 2002 version. In this manufacturing- ready 90nm technology, Intel abandoned the strained-Si channel MOSFET with relaxed SiGe layer that it highlighted in its 2002 paper. Instead, a much less aggressive transistor strain engineering is used for volume manufacturing. f m)pulz.‘阿果资源网(www.agpr.net)版权所有‘
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The PMOS transistor of the volume-manufacturing 90nm technology involves silicon recess etch in the source/drain, and embedding a compressively strained SiGe film in the source/drain regions by selective epitaxy. The resulting uniaxial compressive stress gives a record-high P-ch drive current of 700uA/um at Vdd=1.2V with off-state leakage of 40nA/um. This is ~10% improvement over the already impressive P-ch drive current reported in the IEDM 2002 paper. Wp!%-vzy&.‘阿果资源网(www.agpr.net)版权所有‘
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Stress engineering for NMOS relies on a highly tensile silicon nitride capping layer deposited after silicide formation. With this tensile stress film, Intel was able to maintain the drive current of 1260uA/um, the same value as 2002 that was obtained with the strained-Si channel/SiGe layer approach. In order to maintain the same N-ch drive current in 2003, N-ch gate length was decreased to 45nm from 50nm a year ago. This indicates stress from silicon nitride capping layer is not as effective as using SiGe layer in improving mobility. #t: S.A@.‘阿果资源网(www.agpr.net)版权所有‘
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While companies like IBM, Motorola, and AMD switched to SOI for their high-performance logic technology a generation or two ago, Intel is marching down the technology road map relying on good old bulk CMOS. With bulk CMOS, Intel demonstrates it can do more than matching what SOI can offer. At IEDM 2002, Intel described its bulk CMOS 90nm logic technology with strained-silicon channel MOSFET (S. Thompson, et al., pp. 61-64) using SiGe epitaxial layer. Although this approach was scrapped a year later in its volume-manufacturing 90nm technology, it is significant that the strained silicon channel was used for the first time in the fully integrated CMOS process. naYrpK,..‘阿果资源网(www.agpr.net)版权所有‘
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Highlighted in Intel’s 2002 90nm technology are the strained silicon and nickel silicide. Gate oxide was also aggressively scaled, as it has been in the past. Aggressive gate oxide scaling has been a key in enabling Intel to maintain leadership in transistor performance. For 90nm technology, the physical gate oxide thickness was scaled down to 1.2nm. X(]WV Cu.‘阿果资源网(www.agpr.net)版权所有‘
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Coupled with such a thin gate oxide, strained-silicon MOSFET with a 50nm gate length delivers superb performance. With a strained-silicon channel formed over a relaxed SiGe layer, Intel achieved a higher mobility for both electrons and holes at both low and high vertical fields. At Vdd=1.2V, transistor drive currents for NMOS and PMOS are 1260uA/um and 630uA/um, respectively, with 40nA/um off-state leakage. Intel estimates 10%-20% increase in drive current due to strained silicon. This is the best transistor DC performance reported at the 90nm generation. [E!o QVY.‘阿果资源网(www.agpr.net)版权所有‘
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In order to form a low-resistance silicide on SiGe source and drain, Intel opted NiSi over CoSi at the 90nm node, making a transition to NiSi one generation ahead of other companies. For Intel, this was necessary because of strained silicon. ‘IZI:V" .‘阿果资源网(www.agpr.net)版权所有‘
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The fact that Intel implemented strained silicon at the 90nm node prompts the following speculation. Aggressive gate oxide scaling made Intel rely on a heavily nitrided oxide to suppress gate leakage. At the 90nm node, this probably has caused severe mobility degradation. In order for Intel to stay on its aggressive transistor performance trend curve, Intel needed a significant boost in transistor performance, and strained silicon was its solution. ! ;i`PPRwk.‘阿果资源网(www.agpr.net)版权所有‘
0B@SN)In this 90nm paper, unlike its predecessors, Intel did not disclose ring oscillator stage delay. This also causes a speculation that NMOS and PMOS Idsat values reported in the paper were probably obtained from different processes, optimized for NMOS and PMOS separately. If this is true, integration of the strained-silicon channel MOSFET/SiGe layer into the full CMOS process was not ready at Intel in 2002. T ( OW.‘阿果资源网(www.agpr.net)版权所有‘
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Although DC performance of Intel transistors is the best among the 90nm technologies, the AC performance title at the 90nm node in terms of ring oscillator stage delay goes to IBM, which reported inverter stage delay of 5.0ps at Vdd=1.2V. (See 90nm SOI CMOS Technology by IBM.) q qpgy7.‘阿果资源网(www.agpr.net)版权所有‘
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The back-end process features 7 layers of Cu with low-k (carbon-doped oxide) ILD. The SRAM cell size is a respectable 1um**2. i5Zk_-\#H.‘阿果资源网(www.agpr.net)版权所有‘
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90nm SOI CMOS Technology by IBM As3.Q(#Z.‘阿果资源网(www.agpr.net)版权所有‘
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IBM’s 90nm CMOS technology, presented at the IEDM 2002 (M. Khare, et al., IEDM 2002, pp. 407-410) is an SOI CMOS technology with a silicon film thickness of 45nm. It features SRAM cell size of 0.992um**2, among the most compact in this generation. This small SRAM cell is made possible partly due to the unique features of SOI technology, but the cell is about the same size as Intel’s bulk 90nm technology. 0~ZFv Wv.‘阿果资源网(www.agpr.net)版权所有‘
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Gate dielectric is a heavily nitrided oxide with inversion thickness of 1.85nm and 2.1nm for N-ch and P-ch, respectively. The MOSFET gate length is 46nm. Comparison of SOI transistor DC performance with its bulk counterpart is not straightforward because of self-heating in SOI. Based on IBM’s estimate, Idsat without self-heating for Vcc=1.2V is 1322uA/um and 599uA/um for N-ch and P-ch, respectively. N-ch and P-ch off-state leakage currents are 70nA/um and 80nA/um. This transistor DC performance is among the best at the 90nm node. The benefit of SOI is more pronounced in the AC performance. Unloaded inverter ring oscillator boasts an impressive per-stage delay of 6.1 ps at 1V and 5.0 ps at 1.2V, claimed to be the fastest in the industry at the 90nm node. 12;8 o<~ .‘阿果资源网(www.agpr.net)版权所有‘
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CoSi is used in IBM’s 90nm technology. BEOL features up to 10 levels of Cu interconnect with SiLK low-k dielectric material. Cu damascene process uses Ta-based liner and diffusion barrier, and electroplated Cu. For all critical FEOL and BEOL layers, patterning is carried out with 193nm lithography. bn^ {c.‘阿果资源网(www.agpr.net)版权所有‘
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90nm General-purpose CMOS Technology for SoC Applications by TSMC A%`[mc]4#.‘阿果资源网(www.agpr.net)版权所有‘
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The 90nm technology by TSMC is a multi-purpose bulk CMOS technology that supports low power, ASIC, or high speed SoC applications. For high-speed applications, the gate length is 45nm, and the EOT of heavily nitrided gate oxide is less than 1.4nm. For Vcc=1V, Idsat is 830uA/um and 380uA/um for N-ch and P-ch, respectively, with off-state current of 75nA/um. Unloaded inverter ring oscillator delay is 7.9ps at Vcc=1V. +)y^ ‘ Qs.‘阿果资源网(www.agpr.net)版权所有‘
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Critical layers are defined by 193nm lithography with OPC and PSM. This technology offers SRAM with a cell size as small as 0.999um**2. The back-end process features 9 layers of Cu interconnect and black diamond low-k dielectric, with k less than 3. VH+%ap(~Yx 3$*.‘阿果资源网(www.agpr.net)版权所有‘
90nm CMOS Technology for SoC Applications by Samsung SzjkI+-$:.‘阿果资源网(www.agpr.net)版权所有‘
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Samsung’s 90nm SoC technology is similar to that of TSMC. (See 90nm General-purpose CMOS Technology for SoC Applications by TSMC.) Samsung supports low power, generic (ASIC), and high-speed applications. cUA7#1\T=.‘阿果资源网(www.agpr.net)版权所有‘
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For high-speed applications, the gate length is 50nm, and the gate oxide thickness is 1.3nm. Idsat of high-speed transistors is 850uA/um and360uA/um for N-ch and P-ch, respectively, at Vcc=1V with off-state leakage current of 90nA/um. LN@F+CyDc.‘阿果资源网(www.agpr.net)版权所有‘
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SRAM cell size is competitive at 1.1um**2. Like the majority of other companies, Samsung continues using CoSi at the 90nm node. dvt9u9Vg=.‘阿果资源网(www.agpr.net)版权所有‘
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It is worth noting that high-k dielectric(电介质) is offered for low power applications. HfO2-Al2O3 is used for high-k dielectric, and is deposited by ALD. Although manufacturability remains to be seen, Samsung claims manufacturable SoC technology with high-k dielectric was demonstrated for the first time in the industry. O"F_*.‘阿果资源网(www.agpr.net)版权所有‘
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The back-end process features 9 layers of Cu via-first dual damascene interconnect with SiOC low-k dielectric with k=2.9. !V i@1E.‘阿果资源网(www.agpr.net)版权所有‘
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High Density Embedded SRAM for 90nm Logic Technology by Toshiba y 0‘Rmk,.‘阿果资源网(www.agpr.net)版权所有‘
Toshiba described embedded SRAM for 90nm CMOS at IEDM 2002. With a cell size of 0.8um**2, it is among the smallest SRAM cell reported to date at the 90nm node. (The other is 0.79um**2 from Samsung, reported in IEDM 2002.) One key to achieving this small SRAM cell is the careful optimization of n+ to p+ spacing. High NA 193nm lithography with OPC is also essential to achieving such a small SRAM cell. 2JJ"O|Ibz.‘阿果资源网(www.agpr.net)版权所有‘
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The transistor gate length is conservative at 70nm, and NO-oxynitride is used as gate dielectric. The drive current at Vdd=1.2V is 760uA/um at Ioff=1nA/um for NMOS, and 250uA/um at Ioff=2nA/um for PMOS. Q zlo‘e1.‘阿果资源网(www.agpr.net)版权所有‘
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For this technology, Toshiba continues to use CoSi. The back-end process features Cu interconnect with low-k ILD. dv.(7 Y7.x.‘阿果资源网(www.agpr.net)版权所有‘
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90nm Logic Technology by TI ,)iKH]lY=.‘阿果资源网(www.agpr.net)版权所有‘
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TI unveiled its 90nm bulk CMOS technology at the Symposium on VLSI Technology in June, 2003. It features an aggressively scaled gate length of 37nm, and nitrided gate oxide with EOT of 1.3nm. V\ ^EfQ.‘阿果资源网(www.agpr.net)版权所有‘
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For such a short gate length, TI uses NiSi that maintains a gate poly sheet resistance of less than 10 ohms/sq for a gate length down to ~28nm. NiSi also provides lower S/D contact resistance and better dopant activation. As a result, TI reports an 8% PMOS drive current improvement with NiSi. Pri`K/.‘阿果资源网(www.agpr.net)版权所有‘
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The drive current for NMOS and PMOS is 1040uA/um and 530uA/um, respectively, at Vcc=1.2V with an off-state leakage current of 50nA/um. While this result is good enough for high-performance logic applications, it is not favorable compared with Intel. Idsat of TI is 18% and 16% lower than Intel’s 2002 data for NMOS and PMOS, respectively. 9\]^|?zQ`.‘阿果资源网(www.agpr.net)版权所有‘
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TI did not report ring oscillator stage delay, instead relying on CV/I metric. This suggests, like Intel in IEDM 2002, that TI needs further process optimization of its 90nm CMOS technology to demonstrate good AC performance as well as DC performance. Q~j`Y mR|.‘阿果资源网(www.agpr.net)版权所有‘
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Critical patterns were defined with 193nm lithography. To define short gate lengths of 37nm, model-based OPC with PSM was employed. The back-end process features 9 levels of Cu interconnect with 6 levels of low-k (k=2.8) OSG dielectric. K!]1oy‘V.‘阿果资源网(www.agpr.net)版权所有‘
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130nm Node Logic Technology y T#{UA^.‘阿果资源网(www.agpr.net)版权所有‘
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The majority of companies made a transition from aluminum interconnect to copper interconnect at 130nm node. The 130nm logic technology is currently the most advanced logic technology used in volume production, and will remain so in the 2003-2004 time frame. 5n ^TR B.‘阿果资源网(www.agpr.net)版权所有‘
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130nm Logic Technology by Intel Qo1eXMW.‘阿果资源网(www.agpr.net)版权所有‘
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Intel presented an enhanced version of its 130nm logic technology at the 2001 IEDM. It features 6 layers of Cu interconnect, an improved transistor performance, and 5% linear shrink over the previous 130nm version presented a year earlier. ZD C9oX @.‘阿果资源网(www.agpr.net)版权所有‘
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The SRAM cell size is 2um**2, achieved with 248nm lithography. The transistor gate length is 60nm, and the physical thickness of nitrided gate oxide is 1.5nm. The transistor drive current is 1300uA/um for N-ch and 660uA/um for P-ch at Vdd=1.4V and Ioff=100nA/um. Inverter ring oscillator delay is ~6ps at Vdd=1.4V with Ioff=10nA/um. [*Z`Kc .‘阿果资源网(www.agpr.net)版权所有‘
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The Idsat numbers look impressive, and support Intel’s claim that these are the highest reported in the 130nm generation. In comparison, the drive current of 130nm SOI CMOS technology from IBM is slightly worse than Intel’s when compared at the same Vdd and Idoff, and with a correction for self-heating. (See 130nm SOI CMOS Logic Technology by IBM.) fof2 xcH!.‘阿果资源网(www.agpr.net)版权所有‘
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At the 130nm node, Intel abandoned the notched gate poly that was used at the 180nm node, and returned to a straight sidewall poly. This was not unexpected, because of the issues in scalability and manufacturability associated with notched poly. 34QfgMy H.‘阿果资源网(www.agpr.net)版权所有‘
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The back-end technology features 6 layers of dual damascene Cu interconnect with fluorinated SiO2 as ILD. Fluorinated SiO2 has a k value of 3.6. PjIeZ&p.‘阿果资源网(www.agpr.net)版权所有‘
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130nm SOI CMOS Logic Technology by IBM ?‘r9"M>.‘阿果资源网(www.agpr.net)版权所有‘
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IBM presented its second-generation high performance 0.13um SOI logic technology at IEDM 2001. This was an enhanced version of the first-generation 0.13um SOI technology that IBM presented one and a half years earlier at the Symposium on VLSI Technology 2000. &)pK%SAM.‘阿果资源网(www.agpr.net)版权所有‘
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SRAM cell size is 1.8um**2, the smallest at the 130nm node. This small SRAM cell size was achieved by tight design rules allowed by SOI, and by using 248nm lithography with OPC and RET. /dDzZ%/@.‘阿果资源网(www.agpr.net)版权所有‘
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The transistor DC drive currents at Vdd=1.4V and Ioff=100nA/um are 1100uA/um for N-ch and 625uA/um for P-ch. Drive currents without self-heating are projected to be ~1240uA/um and ~660uA/um for N-ch and P-ch, respectively. e(1k0W4 B.‘阿果资源网(www.agpr.net)版权所有‘
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The ring oscillator speed is quite impressive, demonstrating the benefit of SOI technology. At Vdd=1.2V, inverter stage delay is 5.46ps for Ldesign of 48nm, claimed to be the fastest at 0.13um node at 1.2V. This claim, however, cannot be independently confirmed because of the lack of transistor off-state leakage current data for Ldesign of 48nm. Note that Intel’s inverter delay of ~6ps was quoted at Vdd=1.4V with Ioff=10nA/um. ["3df>!f.‘阿果资源网(www.agpr.net)版权所有‘
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IBM offers 8 layers of Cu damascene interconnect and uses SiLK for low-k ILD. The back-end technology also incorporates an amorphous SiC film with k value of 4.5, deposited by PECVD. SiC film replaces SiN as hard mask and post CMP cap material, allowing IBM to achieve a completely low-k BEOL. sXl ??UGe.‘阿果资源网(www.agpr.net)版权所有‘
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130nm CMOS Platform Logic Technology by IBM, Infineon, and UMC Xy#V Q{!.‘阿果资源网(www.agpr.net)版权所有‘
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Presented 6 months earlier than the 130nm SOI technology presented at the Symposium on VLSI Technology 2001, this is the bulk CMOS platform technology for SoC applications developed jointly by three companies. =sQ(iso%f.‘阿果资源网(www.agpr.net)版权所有‘
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It offers up to 8 levels of Cu interconnect with low-k dielectric (SiLK) with a k value of 2.7. The SRAM cell size is 2.28um**2, ~25% larger than its SOI counterpart. Embedded DRAM with a trench capacitor cell is offered for SoC applications. Analog and RF elements, such as MIM capacitors, precision resistors, inductors, and RF devices are provided for mixed-signal applications. DY>
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MOS technology evolved from PMOS in the 1960’s, to NMOS in 1970’s, and to CMOS in the 1980’s. CMOS technology then became the mainstream IC fabrication technology, and is now the dominant technology for IC manufacturing. I
Integration of one billion transistors into a single chip will become a reality before 2010. Intel’s processor roadmap projects a one billion-transistor chip around 2007. This chip will be built on 45nm CMOS technology with transistors having a gate length of around 25nm. CMOS will remain the dominant technology as industry continues toward the scaling limit. `?\tUO2_T.‘阿果资源网(www.agpr.net)版权所有‘
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As of 2nd half of 2004, 90nm technology is at the beginning of manufacturing life cycle at a very limited number of top semiconductor manufacturers. For majority of IC manufacturers, 90nm technology is in the qualification stage or in the middle of development. ? ]sM8Bd}.‘阿果资源网(www.agpr.net)版权所有‘
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0.13um technology is now in volume production in leading IC manufacturers for high-performance and high-density products. Across the industry, however, 0.18um or older technology is still used for production of many logic products. 5 lKJll^2:.‘阿果资源网(www.agpr.net)版权所有‘
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Development of 65nm technology is now in full swing in the industry. For many companies, it is still in the early stage or in the middle of development. We are already seeing encouraging results on fully integrated 65nm logic technologies from early leaders at 65nm node. There is no sign of slowing down in scaling the logic technology to the 65nm generation. qpoV]#iW.‘阿果资源网(www.agpr.net)版权所有‘
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There are two breeds of logic technology that serve the market today. One is high- performance logic technology, and the other is platform technology. W^,S6!.‘阿果资源网(www.agpr.net)版权所有‘
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High-performance logic technology is aimed at high-speed and high-density applications such as microprocessors, graphics processors, and digital signal processors. The important goal of this kind of technology is to deliver the highest speed performance and density. Aggressive technology scaling, adoption of new processes, and good transistor and interconnect performance are the key attributes of this type of technology, as exemplified by technology from Intel, AMD, and IBM. v 7 .‘阿果资源网(www.agpr.net)版权所有‘
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The platform technology serves multiple applications, such as low power, general purpose (ASIC), RF and mixed signal, and high-performance applications. This technology is modular and flexible, and quite often features embedded memory capability such as DRAM, SRAM, and flash memory. Logic technologies for system-on-chip (SoC) applications belong to this category. For many integrated device manufacturers (IDM) and foundry companies, such as TSMC and UMC, this is the logic technology of choice. a` 9L,8Ve.‘阿果资源网(www.agpr.net)版权所有‘
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The following reviews describe the latest developments in logic technology. })xp%<`.‘阿果资源网(www.agpr.net)版权所有‘
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65nm Node Logic Technology LZPuDf~/.‘阿果资源网(www.agpr.net)版权所有‘
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During the past several years, there have been numerous publications and presentations addressing process and device issues at 65nm node. In 2002, Toshiba became the first company to bring a fully integrated 65nm technology to the public’s attention when it presented 65nm CMOS technology at IEDM 2002. A year later, NEC and Fujitsu joined the 65nm club when they presented their own 65nm logic technologies at IEDM 2003. Other companies, such as IBM, TI, Motorola, TSMC, Samsung, STMicro, presented at conferences the results of integrated 65nm process or features of their 65nm technology in 2003-2004 time frame. Intel is now said to be planning a production start in early 2005. | r ue=QZ.‘阿果资源网(www.agpr.net)版权所有‘
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65nm SoC Technology by Toshiba pEECHk.‘阿果资源网(www.agpr.net)版权所有‘
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The 65nm technology by Toshiba presented at the IEDM 2002 (N. Yanagiya, et al., pp. 57-60) is targeted for SoC application. It features embedded SRAM and DRAM with cell sizes of 0.6um**2 and 0.11um**2, respectively. The DRAM cell has a 6.5um deep trench capacitor that provides 20fF capacitance. -}K<ni6.‘阿果资源网(www.agpr.net)版权所有‘
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The MOSFET gate length is 30nm, which is realized by high-NA 193nm lithography, alternating phase shift mask (PSM), and resist slimming process. Gate dielectric is a nitrided oxide with EOT of ~10A. Poly-SiGe coupled with spike RTA provides adequate activation for gate doping. MOS transistors offer good DC performance; the drive current is 700uA/um for N-ch and 300uA/um for P-ch at Vdd=0.85V with an off-state leakage of 100nA/um. m%?V7-9!k.‘阿果资源网(www.agpr.net)版权所有‘
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At 65nm node, nickel silicide is expected to replace cobalt silicide to achieve low resistance on narrow gate poly lines and also to achieve low junction leakages. Toshiba uses NiSi in its 65nm technology and demonstrates good performance for narrow poly line resistance and junction leakage. 1?Z4 K /.‘阿果资源网(www.agpr.net)版权所有‘
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Critical mask layers are defined with high-NA 193nm lithography with alternating phase shift mask. Toshiba can offer up to 13 layers of Cu interconnect with low-k ILD with a target dielectric constant of 2.7. ut r: J.‘阿果资源网(www.agpr.net)版权所有‘
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Toshiba relies mostly on conventional processes available today, so manufacturability of its 65nm technology is well demonstrated. U(x]O/m .‘阿果资源网(www.agpr.net)版权所有‘
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65nm Technology by NEC ({o‘d=nO.‘阿果资源网(www.agpr.net)版权所有‘
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NEC’s 65nm bulk CMOS technology, presented in IEDM 2003 (Y. Nakahara, et al., pp. 281-284), was developed with emphasis on gate oxide and transistor reliability for a wide range of Vdd operation. Like Toshiba, NEC demonstrates that 65nm node can be reached by extending process technologies available at 90nm node. One new feature at 65nm node is the nickel silicide. Like Toshiba, NEC made a transition from CoSi to NiSi at 65nm node. NF? vg/{.‘阿果资源网(www.agpr.net)版权所有‘
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Gate dielectric is a plasma-nitrided gate oxide with a thickness of 1.1nm/1.35nm for 0.9V/1.2V operation. Nitrogen concentration in the gate oxide was optimized carefully to achieve acceptable gate oxide TDDB, transistor NBTI and HCI lifetime. VH:]@x//{.‘阿果资源网(www.agpr.net)版权所有‘
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The MOSFET gate length is 43nm, patterned by 193nm lithography and ARC shrink etching. NEC achieves good transistor drive currents for platform technology. At Vdd=1.2V, the drive current is 1150uA/um for N-ch and 550uA/um for P-ch with off-state leakage current of 180nA/um. These drive currents are achieved by film stress optimization (tensile stress on N-ch, neutral stress on P-ch) as well as channel, gate, and S/D extension engineering. +U@<\kIF.‘阿果资源网(www.agpr.net)版权所有‘
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65nm Technology for Mobile Multimedia Applications by Fujitsu c ;‘[W60.‘阿果资源网(www.agpr.net)版权所有‘
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Targeted for mobile multimedia applications, Fujitsu’s 65nm technology, presented at IEDM 2003 (S. Nakai, et al., pp. 285-288), focuses on interconnect parasitic capacitance reduction to achieve high-speed data transmission. [V WUqlNt>.‘阿果资源网(www.agpr.net)版权所有‘
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The use of hybrid low-k material, consisting of NSC (nano-clustering silica, a porous silica material) with k=2.25 at wire level and SiOC with k=2.9 at via level, allows Fujitsu to achieve a significant reduction in RC delay and power consumption caused by interconnect capacitance. Simulation results indicate a 25% reduction in interconnect RC delay and a 41% reduction in power consumption when compared with its 90nm technology. Optimization of BEOL provides NSC/SiOC hybrid low-k material with sufficient mechanical strength, resulting in a robust interconnect system. q?ix$nKOv.‘阿果资源网(www.agpr.net)版权所有‘
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The MOSFET features a conservative gate length of 50nm, and EOT is 2.3nm using nitrided oxide. The drive current is acceptable, but not particularly impressive at 65nm node: 830uA/um for N-ch and 350uA/um for P-ch at Vdd=1.1V with off-state leakage current of 30nA/um. @qHNE,K.‘阿果资源网(www.agpr.net)版权所有‘
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Fujitsu’s 65nm technology also features SRAM with a competitive cell size measured at 0.55um**2. A small SRAM cell is achieved by 193nm lithography with NA=0.75, attenuated PSM, and model-based OPC. k{Aj^O3gD.‘阿果资源网(www.agpr.net)版权所有‘
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Like Toshiba and NEC, Fujitsu uses NiSi at 65nm node. The back-end process uses copper interconnect, except for the top layer, for which Fujitsu uses aluminum. `kJ^zw+.‘阿果资源网(www.agpr.net)版权所有‘
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90nm Node Logic Technology ID G}ZlG.‘阿果资源网(www.agpr.net)版权所有‘
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90nm technology took the main stage in 2002. A large number of companies presented their 90nm technologies either at the Symposium on VLSI Technology in June, 2002 or at the IEDM in December, 2002. SK# (#OQoh.‘阿果资源网(www.agpr.net)版权所有‘
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At least nine companies delivered a paper on 90nm or 100nm technology in 2002. These companies include Intel, TSMC, Samsung, Sony, IBM, NEC, Toshiba, Mitsubishi, Matsushita, Fujitsu, and Motorola. For these companies, a major development milestone was reached in this technology node during the 2001-2002 timeframe. However, these are the first-phase development results, and are by no means production ready at the time of presentation. ] A+?EE2/.‘阿果资源网(www.agpr.net)版权所有‘
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A few more 90nm technology presentations followed in 2003, at the Symposium on VLSI Technology and at IEDM. TI joined the 90nm club six months after the first wave of 90nm companies, when it presented 90nm logic technology at the Symposium on VLSI Technology in June, 2003. In December, 2003 at IEDM, Intel described its 90nm technology for volume manufacturing in its late paper presentation. TSMC presented 90nm SoC technology for mixed-signal and RF applications. L>R P-x>.‘阿果资源网(www.agpr.net)版权所有‘
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Intel’s 90nm technology presented at IEDM 2003 is a follow-up to its 90nm paper presented in IEDM 2002. However, it should be noted that, rather than a refinement of its 2002 technology, the volume manufacturing technology described in the 2003 paper was drastically different from 2002 version in the implementation of strained-Si. For the volmue manufacturing 90nm technology, Intel abandons the strained-Si channel approach that it highlighted in the 2002 paper, and opts for a less aggressive strain engineering. (For more details, see 90nm Logic Technology by Intel, 2003 Version below.) q; ][5.‘阿果资源网(www.agpr.net)版权所有‘
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90nm Logic Technology by Intel, 2003 Version m1M t#@,$.‘阿果资源网(www.agpr.net)版权所有‘
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At IEDM 2003, Intel presented 90nm volume manufacturing technology in a late paper (T. Ghani, et al., pp. 978-980). This is a more mature 90nm technology than the one it presented a year ago and also has one significant difference from 2002 version. In this manufacturing- ready 90nm technology, Intel abandoned the strained-Si channel MOSFET with relaxed SiGe layer that it highlighted in its 2002 paper. Instead, a much less aggressive transistor strain engineering is used for volume manufacturing. f m)pulz.‘阿果资源网(www.agpr.net)版权所有‘
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The PMOS transistor of the volume-manufacturing 90nm technology involves silicon recess etch in the source/drain, and embedding a compressively strained SiGe film in the source/drain regions by selective epitaxy. The resulting uniaxial compressive stress gives a record-high P-ch drive current of 700uA/um at Vdd=1.2V with off-state leakage of 40nA/um. This is ~10% improvement over the already impressive P-ch drive current reported in the IEDM 2002 paper. Wp!%-vzy&.‘阿果资源网(www.agpr.net)版权所有‘
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Stress engineering for NMOS relies on a highly tensile silicon nitride capping layer deposited after silicide formation. With this tensile stress film, Intel was able to maintain the drive current of 1260uA/um, the same value as 2002 that was obtained with the strained-Si channel/SiGe layer approach. In order to maintain the same N-ch drive current in 2003, N-ch gate length was decreased to 45nm from 50nm a year ago. This indicates stress from silicon nitride capping layer is not as effective as using SiGe layer in improving mobility. #t: S.A@.‘阿果资源网(www.agpr.net)版权所有‘
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While companies like IBM, Motorola, and AMD switched to SOI for their high-performance logic technology a generation or two ago, Intel is marching down the technology road map relying on good old bulk CMOS. With bulk CMOS, Intel demonstrates it can do more than matching what SOI can offer. At IEDM 2002, Intel described its bulk CMOS 90nm logic technology with strained-silicon channel MOSFET (S. Thompson, et al., pp. 61-64) using SiGe epitaxial layer. Although this approach was scrapped a year later in its volume-manufacturing 90nm technology, it is significant that the strained silicon channel was used for the first time in the fully integrated CMOS process. naYrpK,..‘阿果资源网(www.agpr.net)版权所有‘
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Highlighted in Intel’s 2002 90nm technology are the strained silicon and nickel silicide. Gate oxide was also aggressively scaled, as it has been in the past. Aggressive gate oxide scaling has been a key in enabling Intel to maintain leadership in transistor performance. For 90nm technology, the physical gate oxide thickness was scaled down to 1.2nm. X(]WV Cu.‘阿果资源网(www.agpr.net)版权所有‘
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Coupled with such a thin gate oxide, strained-silicon MOSFET with a 50nm gate length delivers superb performance. With a strained-silicon channel formed over a relaxed SiGe layer, Intel achieved a higher mobility for both electrons and holes at both low and high vertical fields. At Vdd=1.2V, transistor drive currents for NMOS and PMOS are 1260uA/um and 630uA/um, respectively, with 40nA/um off-state leakage. Intel estimates 10%-20% increase in drive current due to strained silicon. This is the best transistor DC performance reported at the 90nm generation. [E!o QVY.‘阿果资源网(www.agpr.net)版权所有‘
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In order to form a low-resistance silicide on SiGe source and drain, Intel opted NiSi over CoSi at the 90nm node, making a transition to NiSi one generation ahead of other companies. For Intel, this was necessary because of strained silicon. ‘IZI:V" .‘阿果资源网(www.agpr.net)版权所有‘
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The fact that Intel implemented strained silicon at the 90nm node prompts the following speculation. Aggressive gate oxide scaling made Intel rely on a heavily nitrided oxide to suppress gate leakage. At the 90nm node, this probably has caused severe mobility degradation. In order for Intel to stay on its aggressive transistor performance trend curve, Intel needed a significant boost in transistor performance, and strained silicon was its solution. ! ;i`PPRwk.‘阿果资源网(www.agpr.net)版权所有‘
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Although DC performance of Intel transistors is the best among the 90nm technologies, the AC performance title at the 90nm node in terms of ring oscillator stage delay goes to IBM, which reported inverter stage delay of 5.0ps at Vdd=1.2V. (See 90nm SOI CMOS Technology by IBM.) q qpgy7.‘阿果资源网(www.agpr.net)版权所有‘
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The back-end process features 7 layers of Cu with low-k (carbon-doped oxide) ILD. The SRAM cell size is a respectable 1um**2. i5Zk_-\#H.‘阿果资源网(www.agpr.net)版权所有‘
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90nm SOI CMOS Technology by IBM As3.Q(#Z.‘阿果资源网(www.agpr.net)版权所有‘
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IBM’s 90nm CMOS technology, presented at the IEDM 2002 (M. Khare, et al., IEDM 2002, pp. 407-410) is an SOI CMOS technology with a silicon film thickness of 45nm. It features SRAM cell size of 0.992um**2, among the most compact in this generation. This small SRAM cell is made possible partly due to the unique features of SOI technology, but the cell is about the same size as Intel’s bulk 90nm technology. 0~ZFv Wv.‘阿果资源网(www.agpr.net)版权所有‘
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Gate dielectric is a heavily nitrided oxide with inversion thickness of 1.85nm and 2.1nm for N-ch and P-ch, respectively. The MOSFET gate length is 46nm. Comparison of SOI transistor DC performance with its bulk counterpart is not straightforward because of self-heating in SOI. Based on IBM’s estimate, Idsat without self-heating for Vcc=1.2V is 1322uA/um and 599uA/um for N-ch and P-ch, respectively. N-ch and P-ch off-state leakage currents are 70nA/um and 80nA/um. This transistor DC performance is among the best at the 90nm node. The benefit of SOI is more pronounced in the AC performance. Unloaded inverter ring oscillator boasts an impressive per-stage delay of 6.1 ps at 1V and 5.0 ps at 1.2V, claimed to be the fastest in the industry at the 90nm node. 12;8 o<~ .‘阿果资源网(www.agpr.net)版权所有‘
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CoSi is used in IBM’s 90nm technology. BEOL features up to 10 levels of Cu interconnect with SiLK low-k dielectric material. Cu damascene process uses Ta-based liner and diffusion barrier, and electroplated Cu. For all critical FEOL and BEOL layers, patterning is carried out with 193nm lithography. bn^ {c.‘阿果资源网(www.agpr.net)版权所有‘
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90nm General-purpose CMOS Technology for SoC Applications by TSMC A%`[mc]4#.‘阿果资源网(www.agpr.net)版权所有‘
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The 90nm technology by TSMC is a multi-purpose bulk CMOS technology that supports low power, ASIC, or high speed SoC applications. For high-speed applications, the gate length is 45nm, and the EOT of heavily nitrided gate oxide is less than 1.4nm. For Vcc=1V, Idsat is 830uA/um and 380uA/um for N-ch and P-ch, respectively, with off-state current of 75nA/um. Unloaded inverter ring oscillator delay is 7.9ps at Vcc=1V. +)y^ ‘ Qs.‘阿果资源网(www.agpr.net)版权所有‘
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Critical layers are defined by 193nm lithography with OPC and PSM. This technology offers SRAM with a cell size as small as 0.999um**2. The back-end process features 9 layers of Cu interconnect and black diamond low-k dielectric, with k less than 3. VH+%a
90nm CMOS Technology for SoC Applications by Samsung SzjkI+-$:.‘阿果资源网(www.agpr.net)版权所有‘
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Samsung’s 90nm SoC technology is similar to that of TSMC. (See 90nm General-purpose CMOS Technology for SoC Applications by TSMC.) Samsung supports low power, generic (ASIC), and high-speed applications. cUA7#1\T=.‘阿果资源网(www.agpr.net)版权所有‘
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For high-speed applications, the gate length is 50nm, and the gate oxide thickness is 1.3nm. Idsat of high-speed transistors is 850uA/um and360uA/um for N-ch and P-ch, respectively, at Vcc=1V with off-state leakage current of 90nA/um. LN@F+CyDc.‘阿果资源网(www.agpr.net)版权所有‘
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SRAM cell size is competitive at 1.1um**2. Like the majority of other companies, Samsung continues using CoSi at the 90nm node. dvt9u9Vg=.‘阿果资源网(www.agpr.net)版权所有‘
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It is worth noting that high-k dielectric(电介质) is offered for low power applications. HfO2-Al2O3 is used for high-k dielectric, and is deposited by ALD. Although manufacturability remains to be seen, Samsung claims manufacturable SoC technology with high-k dielectric was demonstrated for the first time in the industry. O"F_*.‘阿果资源网(www.agpr.net)版权所有‘
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The back-end process features 9 layers of Cu via-first dual damascene interconnect with SiOC low-k dielectric with k=2.9. !V i@1E.‘阿果资源网(www.agpr.net)版权所有‘
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High Density Embedded SRAM for 90nm Logic Technology by Toshiba y 0‘Rmk,.‘阿果资源网(www.agpr.net)版权所有‘
Toshiba described embedded SRAM for 90nm CMOS at IEDM 2002. With a cell size of 0.8um**2, it is among the smallest SRAM cell reported to date at the 90nm node. (The other is 0.79um**2 from Samsung, reported in IEDM 2002.) One key to achieving this small SRAM cell is the careful optimization of n+ to p+ spacing. High NA 193nm lithography with OPC is also essential to achieving such a small SRAM cell. 2JJ"O|Ibz.‘阿果资源网(www.agpr.net)版权所有‘
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The transistor gate length is conservative at 70nm, and NO-oxynitride is used as gate dielectric. The drive current at Vdd=1.2V is 760uA/um at Ioff=1nA/um for NMOS, and 250uA/um at Ioff=2nA/um for PMOS. Q zlo‘e1.‘阿果资源网(www.agpr.net)版权所有‘
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For this technology, Toshiba continues to use CoSi. The back-end process features Cu interconnect with low-k ILD. dv.(7 Y7.x.‘阿果资源网(www.agpr.net)版权所有‘
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90nm Logic Technology by TI ,)iKH]lY=.‘阿果资源网(www.agpr.net)版权所有‘
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TI unveiled its 90nm bulk CMOS technology at the Symposium on VLSI Technology in June, 2003. It features an aggressively scaled gate length of 37nm, and nitrided gate oxide with EOT of 1.3nm. V\ ^EfQ.‘阿果资源网(www.agpr.net)版权所有‘
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For such a short gate length, TI uses NiSi that maintains a gate poly sheet resistance of less than 10 ohms/sq for a gate length down to ~28nm. NiSi also provides lower S/D contact resistance and better dopant activation. As a result, TI reports an 8% PMOS drive current improvement with NiSi. Pri`K/.‘阿果资源网(www.agpr.net)版权所有‘
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The drive current for NMOS and PMOS is 1040uA/um and 530uA/um, respectively, at Vcc=1.2V with an off-state leakage current of 50nA/um. While this result is good enough for high-performance logic applications, it is not favorable compared with Intel. Idsat of TI is 18% and 16% lower than Intel’s 2002 data for NMOS and PMOS, respectively. 9\]^|?zQ`.‘阿果资源网(www.agpr.net)版权所有‘
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TI did not report ring oscillator stage delay, instead relying on CV/I metric. This suggests, like Intel in IEDM 2002, that TI needs further process optimization of its 90nm CMOS technology to demonstrate good AC performance as well as DC performance. Q~j`Y mR|.‘阿果资源网(www.agpr.net)版权所有‘
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Critical patterns were defined with 193nm lithography. To define short gate lengths of 37nm, model-based OPC with PSM was employed. The back-end process features 9 levels of Cu interconnect with 6 levels of low-k (k=2.8) OSG dielectric. K!]1oy‘V.‘阿果资源网(www.agpr.net)版权所有‘
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130nm Node Logic Technology y T#{UA^.‘阿果资源网(www.agpr.net)版权所有‘
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The majority of companies made a transition from aluminum interconnect to copper interconnect at 130nm node. The 130nm logic technology is currently the most advanced logic technology used in volume production, and will remain so in the 2003-2004 time frame. 5n ^TR B.‘阿果资源网(www.agpr.net)版权所有‘
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130nm Logic Technology by Intel Qo1eXMW.‘阿果资源网(www.agpr.net)版权所有‘
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Intel presented an enhanced version of its 130nm logic technology at the 2001 IEDM. It features 6 layers of Cu interconnect, an improved transistor performance, and 5% linear shrink over the previous 130nm version presented a year earlier. ZD C9oX @.‘阿果资源网(www.agpr.net)版权所有‘
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The SRAM cell size is 2um**2, achieved with 248nm lithography. The transistor gate length is 60nm, and the physical thickness of nitrided gate oxide is 1.5nm. The transistor drive current is 1300uA/um for N-ch and 660uA/um for P-ch at Vdd=1.4V and Ioff=100nA/um. Inverter ring oscillator delay is ~6ps at Vdd=1.4V with Ioff=10nA/um. [*Z`Kc .‘阿果资源网(www.agpr.net)版权所有‘
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The Idsat numbers look impressive, and support Intel’s claim that these are the highest reported in the 130nm generation. In comparison, the drive current of 130nm SOI CMOS technology from IBM is slightly worse than Intel’s when compared at the same Vdd and Idoff, and with a correction for self-heating. (See 130nm SOI CMOS Logic Technology by IBM.) fof2 xcH!.‘阿果资源网(www.agpr.net)版权所有‘
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At the 130nm node, Intel abandoned the notched gate poly that was used at the 180nm node, and returned to a straight sidewall poly. This was not unexpected, because of the issues in scalability and manufacturability associated with notched poly. 34QfgMy H.‘阿果资源网(www.agpr.net)版权所有‘
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The back-end technology features 6 layers of dual damascene Cu interconnect with fluorinated SiO2 as ILD. Fluorinated SiO2 has a k value of 3.6. PjIeZ&p.‘阿果资源网(www.agpr.net)版权所有‘
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130nm SOI CMOS Logic Technology by IBM ?‘r9"M>.‘阿果资源网(www.agpr.net)版权所有‘
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IBM presented its second-generation high performance 0.13um SOI logic technology at IEDM 2001. This was an enhanced version of the first-generation 0.13um SOI technology that IBM presented one and a half years earlier at the Symposium on VLSI Technology 2000. &)pK%SAM.‘阿果资源网(www.agpr.net)版权所有‘
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SRAM cell size is 1.8um**2, the smallest at the 130nm node. This small SRAM cell size was achieved by tight design rules allowed by SOI, and by using 248nm lithography with OPC and RET. /dDzZ%/@.‘阿果资源网(www.agpr.net)版权所有‘
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The transistor DC drive currents at Vdd=1.4V and Ioff=100nA/um are 1100uA/um for N-ch and 625uA/um for P-ch. Drive currents without self-heating are projected to be ~1240uA/um and ~660uA/um for N-ch and P-ch, respectively. e(1k0W4 B.‘阿果资源网(www.agpr.net)版权所有‘
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The ring oscillator speed is quite impressive, demonstrating the benefit of SOI technology. At Vdd=1.2V, inverter stage delay is 5.46ps for Ldesign of 48nm, claimed to be the fastest at 0.13um node at 1.2V. This claim, however, cannot be independently confirmed because of the lack of transistor off-state leakage current data for Ldesign of 48nm. Note that Intel’s inverter delay of ~6ps was quoted at Vdd=1.4V with Ioff=10nA/um. ["3df>!f.‘阿果资源网(www.agpr.net)版权所有‘
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IBM offers 8 layers of Cu damascene interconnect and uses SiLK for low-k ILD. The back-end technology also incorporates an amorphous SiC film with k value of 4.5, deposited by PECVD. SiC film replaces SiN as hard mask and post CMP cap material, allowing IBM to achieve a completely low-k BEOL. sXl ??UGe.‘阿果资源网(www.agpr.net)版权所有‘
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130nm CMOS Platform Logic Technology by IBM, Infineon, and UMC Xy#V Q{!.‘阿果资源网(www.agpr.net)版权所有‘
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Presented 6 months earlier than the 130nm SOI technology presented at the Symposium on VLSI Technology 2001, this is the bulk CMOS platform technology for SoC applications developed jointly by three companies. =sQ(iso%f.‘阿果资源网(www.agpr.net)版权所有‘
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It offers up to 8 levels of Cu interconnect with low-k dielectric (SiLK) with a k value of 2.7. The SRAM cell size is 2.28um**2, ~25% larger than its SOI counterpart. Embedded DRAM with a trench capacitor cell is offered for SoC applications. Analog and RF elements, such as MIM capacitors, precision resistors, inductors, and RF devices are provided for mixed-signal applications. DY>
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Triple-gate oxide is implemented in the process to meet high-performance, low-power and I/O requirements. For high-performance transistors having 18A gate oxide, the drive current is 810uA/um and 365uA/um for N-ch and P-ch at Vdd=1.2V and Ioff=30nA/um and inverter ring oscillator delay 10ps. 3t .‘阿果资源网(www.agpr.net)版权所有‘
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130nm CMOS Technology by TSMC a!.!2a&t.‘阿果资源网(www.agpr.net)版权所有‘
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TSMC originally described its 130nm CMOS foundry technology at IEDM 2000. One and a half years later at the Symposium on VLSI Technology in June 2002, TSMC presented enhanced 130nm CMOS technology with improved transistor performance and new features to support mixed-signal and RF applications. szn%wZW.‘阿果资源网(www.agpr.net)版权所有‘
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In the new and enhanced 130nm technology, TSMC delivers competitive transistor drive currents. At Vdd=1.2V, Idsat is 870uA/um and 410uA/um for N-ch and P-ch with Ioff=15nA/um. At Vdd=1.4V, those increase to 1100uA/um and 550uA/um, respectively. >PH< N.‘阿果资源网(www.agpr.net)版权所有‘
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TSMC claims that it achieved the best Ion-Ioff at Vdd=1.2V for 130nm technology. TSMC’s drive currents at 1.2V are indeed impressive, and are better than the IBM 130nm bulk CMOS technology that IBM presented a year earlier. Although this claim cannot be independently confirmed because of differences in Vdd and Ioff quoted by Intel and TSMC, the reports by TSMC in this paper put them among the top in the industry. Inverter delay is 10ps at Vdd=1.2V with Ioff=15nA/um, which is comparable to the IBM 130nm platform technology. vUfO4yfdg.‘阿果资源网(www.agpr.net)版权所有‘
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SRAM cell sizes range from 2.43um**2 to 2.9um**2. 193nm lithography was used for the critical layers, while 248nm is used for non-critical layers. The back-end process offers up to 9 layers of Cu interconnect with low-k ILD. 4`G=q^GL,.‘阿果资源网(www.agpr.net)版权所有‘
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130nm CMOS Technology by Hitachi dff#{.‘阿果资源网(www.agpr.net)版权所有‘
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Hitachi described its 130nm CMOS technology for SoC applications at IEDM 2000. The most impressive feature in Hitachi 130nm technology is the SRAM cell size. With a size of 1.92um**2, Hitachi’s SRAM cell is the smallest in the industry at 130nm node for bulk CMOS technology. This small cell size is obtained with 2 additional masks for the well doping of SRAM array, which results in a higher punch-through voltage between n+ and N-well. zlN+edgY#,.‘阿果资源网(www.agpr.net)版权所有‘
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With 1.5nm gate oxide, the transistor drive current is 870uA/um for N-ch and 330uA/um for P-ch at Vdd=1.2V with Ioff=10nA/um.
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射频半导体工艺大全－ED China
各家公司重疾险对癌症定义比较
宁波的各家美食
人的简单总结
人的简单总结
医疗半导体技术和市场的发展趋势分析
比较简单的排毒方法
比较简单的排毒方法
奥迪Q5国产和进口车简单比较
SBR工艺总结
这些年来的简单总结
管理学的简单规律总结
UV喷涂工艺的应用和市场分析
低压绝缘材料的生产工艺和配方工艺
风语者 : 东西方酷刑的简单比较
最全面最简单实用的育儿经验和绝招45条总结
简单比较抗战和抗美援朝谁更出色
半导体公司成功的秘密
WinNT和Linux的比较
Log4j和JDBMonitor的比较